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The dual UA
Active Interface Module supports both Master and Slave (relative to the UA
link) configurations. There are two modes of operation:
Mode
SIM: Active Link Simulation (RX,
TX, RX, TX)
Mode MON:
Active Link Monitoring (RX/TX,
RX/TX)
The interface module can
process eight independent timeslots with configurable bandwidth (default
64 Kbit/s). This corresponds to 4 bi-directional timeslots on a physical
interface in both mode SIM and mode MON. The module provides:
Point-to-point
Two-wires
"ping-pong" configurations
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Feature
Summary
- WAL2 coding/decoding
differential stage
- Full S/W configuration of the
line interface (Mode SIM, Mode MON)
- On-board power feeding (no external devices needed)
- Advanced "Future
Connector" interface to B-channel switch boards
- Clock recovery (SLAVE), system
clock (MASTER) synchronization schemes
- Non-disturbing line interface
through active monitoring
- On-board CODEC for dual
channel voice monitoring
- CE compliant advanced design
using latest manufacturing techniques
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Functionality
The UA
Active Interface Module is a six layer double-sided PCB using auto-assembly SMD
technology according to ISO 9001. The UA
physical interface is isolated from the processor sub-system and uses
independent grounds to block interference.
Additional
Design Features
- 32 bit embedded processor operating at
35 MIPs
- 8 MB of 32 bit wide on board DRAM
- I/O mapped buffered ISA bus transfer
using hardware semaphores
- Self-test diagnostics
- Run-time software image downloaded from
Host
- "Virtual Circuit" design
10.000 gates downloaded from Host
- Software and hardware updates via
Internet
- "Virtual Circuit" allows
customization on request
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